1. Field of the Invention
This invention generally relates to a semiconductor integrated circuit having a data output buffer, and in particular, it relates to a semiconductor integrated circuit wherein circuit malfunction is prevented by reducing the potential fluctuations generated at the power source of the circuit components during data output.
2. Description of the Prior Art
This application is related to a commonly assigned application entitled "Data Output Circuit" filed Mar. 11, 1988 and assigned Ser. No. 167,081. This application is also related to commonly assigned application Ser. No. 023,577 entitled "Buffer Circuit" filed on Mar. 9, 1987.
In semiconductor integrated circuits such as semiconductor memories, the prevention of circuit malfunction due to potential fluctuations in the power source is very important. Such potential fluctuations are generated when data is output from a data output buffer provided at the output stage of, for example, a semiconductor memory. During high-speed access, the output load must be rapidly charged and discharged. During this charging and discharging, potential fluctuations, i.e. power source noise, are generated in the power source and reference potentials respectively. These fluctuations may lead to malfunction of the semiconductor integrated circuit.
FIG. 1 is a circuit diagram of a conventional semiconductor integrated circuit such as a semiconductor memory. In the Figure, the area enclosed by broken lines contains the semiconductor circuit components and the associated output buffer. These semiconductor circuit components may include memory cells, address circuitry, sensing amplifiers, and circuitry for driving the output buffers. It is generally understood that output buffers do not comprise a portion of the internal semiconductor components. This convention will be observed in what follows, i.e., the output buffer is considered distinct from the internal semiconductor circuit components. T1 is a data output pad. T2 is a power source pad supplied with power source voltage V.sub.DD. T3 is a reference pad supplied with reference voltage V.sub.SS. I/O and I/O are internal data buses. MOS transistor 11 is a data output buffer for high-level output and MOS transistor 12 is a data output buffer for low-level output. Transistors 11 and 12 comprise an output switching means for coupling the circuit components to output terminal pad T1. AND gates 13 and 14 control the respective data outputs and comprise circuitry for driving the output buffers. Wiring 15 is associated with source voltage V.sub.DD and wiring 16 is associated with reference voltage V.sub.SS. External D.C. power source 17 feeds power source voltage V.sub.DD to the integrated circuit. Capacitance 18 stabilizes power source 17. Load capacitance 19 is driven by the output data of the integrated circuit. External wiring and lead frame part 20 and bonding wire 21 couple data output pad T1 with load capacitance 19. Lead frame and external wiring part 22 and bonding wire 23 couple external D.C. power source 17 and power source pad T2. Lead frame and external wiring part 24 and bonding wire 25 couple external D.C. power source 17 with reference pad T3. Parasitic inductive and resistive components are present in lead frame and external wiring parts 20, 22, 24 and parasitic inductive components are present in bonding wires 21, 23, and 25. Parasitic resistive components are present in internal wirings 15 and 16.
When such an integrated circuit outputs high-level data, internal data bus I/O becomes level "1" while I/O becomes level "0". Subsequently, the internal control signal .phi. out rises to a level "1" causing the output signal of AND gate 13 to become a level "1". As a result, transistor 11 for high-level output, whose source and drain are inserted between power source pad T2 and data output pad T1, is turned on and conducts. Thus, node N1 at one end of load capacitance 19 gradually charges to a level "1" through transistor 11 and pad T1 as shown by the waveform of FIG. 2. During this process, "undershoot" of the power source voltage V.sub.DD occurs at node N2 as shown by the waveform of FIG. 2. This undershoot is potential fluctuations produced by the inductive and resistive components present in the lead frame and external wiring part 22, bonding wire 23 and internal wiring 15. The same undershoot also occurs at node N3 of wiring 16 on the reference voltage side.
In a similar manner, when low-level data is to be output, internal data bus I/O becomes level "0", while I/O becomes level "1". Subsequently, the internal control signal .phi. out rises to level "1", causing the output signal of AND gate 14 to become a level "1". As a result, transistor 12 for low-level output, whose source and drain are inserted between data output pad T1 and reference pad T3, is turned on and conducts. Thus, by the discharge of load capacitance 19, node N1 at one end thereof gradually discharges through transistor 12 and pad T1 to a level "0" as shown by the waveform of FIG. 3. During this process, "overshoot" of the reference voltage V.sub.SS occurs at node N3 as shown by the waveform of FIG. 3. This overshoot is potential fluctuations produced by the inductive and resistive components present in the lead frame and external wiring part 24, bonding wire 25 and internal wiring 16. The same overshoot also occurs at node N2 of wiring 15 on the power source voltage side. In general, because of the rapid discharge of the load capacitance, overshoot is a more serious problem than undershoot with potential fluctuations of greater magnitude over shorter time intervals.
Such power source noise may cause malfunction of the integrated circuit components and may also interfere with the stability of the external power source system, creating other undesirable effects.